|
The SERDES-VR is designed to be used as a verification tool
for Serializer-Deserializer block with 8b/10b encoder and
decoder. In receiver side, the clock recovery block recovers
the clock from the serial data signal. Synchronization
parameters are programmable to user for various designs.
Transmit side also provides in-detail control for signal
transmission, including jitter and noise insertion for
erroneous case. For testing purpose, loopback and other
testing features are also implemented. Inside SERDES-VR,
8b/10b encoder and decoder logic are implemented which can
be used for any 8b/10b applications.
The interfaces to the BFM are designed to maximize
portability to wide spectrum of designs such that
-
Serial interface with serial data signals only
-
Serial interface with referece serial clock for
supporting fast synchronization
-
Parallel interface with 8-bit data
-
Parallel interface with 10-bit encoded data
-
Parallel interface with 16-bit data (double wide 8-bit
interface)
-
Parallel interface with 20-bit data (double wide 10-bit
interface)
The interface to the design under test is designed to
support various protocols, including
Serdes-VR is available both in
source code and binary format.
-
Receive Features
• Clock recovery from the serial data signal
• Comma detection and word alignment
• Word synchronization status notification
• Electric idle state detection
• Code error and disparity error indication
• Data and K-character indication to design under test
• Loopback incoming data to transmit line
• Dynamic rate adjustment as in PCI-Express 2.0
-
Transmit Features
• 8b/10b encoding and error injection such as
code/disparity anomaly
• Jitter insertion in serial line
• Electric idle state assertion
• Invalid code or disparity word transmission for error
injection
• Dynamic clock rate change as in PCI-Express 2.0
|
