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It is never easy to verify an ASIC that has SATA interfaces
until now. At the transport layer and above, SATA-VR
includes a real ATA/ATAPI device driver that has proven its
value with so many existing ATA/ATAPI devices. There is no
need to worry about backward compatibility. Moreover, three sets of APIs at the
transport, ATA/SATA register, and command layers give you the
capability for full customization. All the advanced and/or
optional features listed in the specification,
are supported.
At the data link and physical layers, SATA-VR has full
implementations of the power-on sequence state machine,
power management state machine, and data
link layer state machine. A functional coverage reporting
mechanism shows how well the state machines are exercised.
With the coverage report and test case automation feature,
you can verify both the physical and data link layers with optimized high-quality
test cases. Moreover, at the physical layer, a full functional serdes model that has clock/data
recovery circuit and clock de-skew on the receive side and the transmission jitter and clock skew
generation on the transmit side is included.
With the backward-compatible driver, the rich set of APIs, fully
automated coverage for the state machines,
SATA-VR can be integrated and customized to match the
uniqueness of any ASIC with ease.
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Full compliance with the latest specification (SATA 2.6)
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Support any clock speed
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Support serdes and PCS interfaces
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Support realistic clock jitter and skew verification
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Support both driving and monitoring functions
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Support all ATA/ATAPI commands
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Support Native Command Queuing
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Multi-threaded for realistic NCQ verification
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Full function serdes model plus tx jitter and skew
injections
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Automatic Physical Power-On Sequence State Machine Exerciser and Monitor
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Automatic Power Management State Machine Exerciser and
Monitor
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Automatic Data Link Layer State Machine Exerciser and
Monitor
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Automatic Transport Layer FIS Exerciser and Monitor
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Device model supports disk/flash model with any size
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Host model includes 32 T13 1510D-compatible DMA engines
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Host model includes a de-facto standard ATA/ATAPI
driver
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Support "first-silicon success" verification with real
ATA/ATAPI Linux driver
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Support Error injection at all layers
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C/Verilog/SystemVerilog APIs at transport layer,
register layer, and ATA/ATAPI command layer
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Full functional coverage grading for state machines at physical and data link layers
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Compliance Suite: A complete set of ATA/ATAPI Command
Layer Protocol Testing
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