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Plug&Play verification.
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Sophisticated
LTSSM state
exerciser automatically and exhaustively performs
endless state transition looping.
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Supports
for parallel, 8/16-bit PIPE, 10/20-bit PCS, and serial
interfaces.
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Supports all Gen2 new features, such as speed
change, up configure, modified polling compliance,
etc.
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Fully
modeled the logical sub-block.
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Supports x1, x2, x4, x8, x12, x16, and x32 lanes in run-time.
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Automatic link training
and initialization or bypass.
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Supports for lane to lane skew/de-skew, lane reversal,
and link error recovery, etc.
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Supports multi-level error injections down to any bit
with powerful automatic control without programming.
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Supports for clock jitter effect and elastic buffer model.
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Automatic and configurable L0s/L1 exit latency
calculation.
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LTSSM state exerciser example source code for DUT.
Running From State to State Endlessly
and Thoroughly
LTSSM State Exerciser Exhaustively Loops Through All
the States
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