PCIE-VR Lite

The Lite version of PCIE-VR is for FPGA designers who need to verify DMA and other sophisticated features before downloading the bit streams. Debugging FPGA in the lab is very time consuming. PCIE-VR Lite can be used as a full functional root complex, bridge, or end point. You can be confident that your design will work before going to the lab.

Not only can you integrate PCIE-VR Lite onto an existing test bench in a few hours, you can also choose your favorite language, either Verilog, System Verilog, or C, to configure your design. Use PCIE-VR Lite to replace any simplified root complex and/or the IP core on your test bench. This speeds up the simulation many folds.

Features

• PCIE standard version Gen1(1.0a, 1.1) and Gen2 (Final)

• Standard interfaces, serial, PIPE, 8/10b, and parallel

• Running on Linux, SunOS, and Windows

• Programming API in Verilog, SystemVerilog, and C

• IP core accelerator

  • Speed up 30X when both root complex and end point are replaced

  • Verified with Xilinx End Point Plus

• Automatic multi-threaded TLP generation without programming