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The Lite version of PCIE-VR is for FPGA designers who need
to verify DMA and other sophisticated features before
downloading the bit streams. Debugging FPGA in the lab is
very time consuming. PCIE-VR Lite can be used as a full
functional root complex, bridge, or end point. You can be
confident that your design will work before going to the
lab.
Not only can you integrate PCIE-VR Lite onto an existing
test bench in a few hours, you can also choose your favorite
language, either Verilog, System Verilog, or C, to configure
your design. Use PCIE-VR Lite to replace any simplified root
complex and/or the IP core on your test bench. This speeds
up the simulation many folds.
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PCIE
standard version Gen1(1.0a, 1.1) and Gen2 (Final)
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Standard interfaces, serial, PIPE, 8/10b, and parallel
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Running on Linux, SunOS, and Windows
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Programming API in Verilog, SystemVerilog, and C
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IP core accelerator
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Automatic multi-threaded TLP generation without
programming
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