PCIE-VR Lite

 

The Lite version of PCIE-VR is for FPGA designers who need to verify DMA and other sophisticated features before downloading the bit streams. Debugging FPGA in the lab is very time consuming. PCIE-VR Lite can be used as a full functional root complex, bridge, or end point. You can be confident that your design will work before going to the lab.

 

Not only can you integrate PCIE-VR Lite onto an existing test bench in a few hours (plug&play), you can also choose your favorite language, either Verilog, System Verilog, or C, to configure your design and write tests. Moreover, using PCIE-VR Lite to replace an encrypted/simplified root complex and/or the IP core on your test bench speeds up the simulation many folds.

Features

  1. PCIE standard version Gen1(1.0a, 1.1) and Gen2 (Final)

  2. Standard interfaces, serial, PIPE, 8/10b, and parallel

  3. Root complex is a complete CPU sub-system

    • Sparse memory model included

    • Support any Verification language

    • Multi-Threaded

  4. Running on Linux, SunOS, and Windows

  5. Programming API in Verilog, SystemVerilog, and C

  6. IP core accelerator

    • Speed up 30X when both root complex and end point are replaced

  7. Automatic multi-threaded TLP generation without programming

    • Bar initialization thread

    • Performance measurement

    • Advanced TLP verification

    • Source code available for adding DUT-specific DMA initialization

For Xilinx Users

  1. Plug&Play verification environments for Xilinx PCIE IP cores

    • Including test bench files, scripts, and a powerful universal makefile for compilation, simulation, regression in parallel, and reporting

    • One executable for all the tests in regression

    • TRN interface for DUT

      • Powerful user application module for performance analysis, implement DUT architecture in SystemC, running system software and driver in C/C++, etc. All can be done before RTL is ready.

    • Best performance in both compilation and simulation. If you can find an environment that runs faster, contact us for a full refund.

  2. Verified with the following Xilinx PCIE IP cores:

    • End Point V3.6 (4 and 8 lanes)

    • End Point Block Plus V1.6 (1, 4, and 8 lanes), V1.10 (4 lanes)

    • End Point PIPE V1.7 (1 lane)

 

 
Copyright 2005 Tarek Verification Systems. All rights reserved.