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The Lite version of PCIE-VR is for FPGA designers who need
to verify DMA and other sophisticated features before
downloading the bit streams. Debugging FPGA in the lab is
very time consuming. PCIE-VR Lite can be used as a full
functional root complex, bridge, or end point. You can be
confident that your design will work before going to the
lab.
Not only can you integrate PCIE-VR Lite onto an existing
test bench in a few hours (plug&play), you can also choose your favorite
language, either Verilog, System Verilog, or C, to configure
your design and write tests. Moreover, using PCIE-VR Lite to replace an
encrypted/simplified root
complex and/or the IP core on your test bench speeds
up the simulation many folds.
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PCIE
standard version Gen1(1.0a, 1.1) and Gen2 (Final)
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Standard interfaces, serial, PIPE, 8/10b, and parallel
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Root
complex is a complete CPU sub-system
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Running on Linux, SunOS, and
Windows
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Programming API in Verilog, SystemVerilog, and C
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IP core accelerator
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Automatic multi-threaded TLP generation without
programming
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Bar initialization thread
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Performance measurement
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Advanced TLP verification
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Source code available for adding DUT-specific DMA
initialization
For Xilinx Users
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Plug&Play verification environments for Xilinx
PCIE IP cores
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Including test bench files, scripts, and a
powerful universal makefile for compilation,
simulation, regression in parallel, and reporting
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One executable for all the tests in regression
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TRN interface for DUT
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Powerful user application module for
performance analysis, implement DUT architecture in SystemC,
running system software and driver in C/C++, etc. All can be
done before RTL is ready.
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Best performance in both compilation and simulation. If you can find an environment that
runs faster, contact us for a full refund.
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Verified with
the following Xilinx PCIE IP cores:
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End Point V3.6 (4 and 8 lanes)
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End Point Block Plus V1.6 (1, 4, and 8 lanes), V1.10 (4
lanes)
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End Point PIPE V1.7 (1 lane)
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